Course Schedlue

## Course Schedlue

Month	Day	Lecture
May	25	Overview: Digital Logic Design Methodology
June	01	VHDL
June	08	VHDL
June	15	VHDL
June	22	VHDL
June	29	Synthesis in Verilog
July	06	Synthesis in VHDL
July	13	Design and synthesis
July	20	Design and synthesis
July	27	Post-synthesis
Aug	03	Post-synthesis
Aug	10	Post-synthesis
Aug	17	Post-synthesis
Aug	24	Post-synthesis
Aug	31	Post-synthesis
Sep	07	Post-synthesis