Advanced Digital Systems Design (PUE 3141) - Summer 2022

PAN AFRICAN UNIVERSITY INSTITUTE FOR BASIC SCIENCES, TECHNOLOGY AND INNOVATION

Announcements

Please check this page frequently for important announcements regarding course work. IMPORTANT!

Teaching Staff

  • Instructors:-
  • Dr. Ahmed A.Rahman A. Ali,
  • Dr. Mutugi Kiruki,
  • Demonstrator: Eng.

Section Hours

Section Day Time Slot Place
1 Wednesday 1st(8.30 - 11.30) Computer Lab 1
2 Wednesday 4rd(2.30 - 5.30) Computer Lab 1

Office Hours

Day Time
xxxday from 9am to 12pm
xxxday from 1pm to 4pm
  • For requesting additional on-line discussion requested via E-Mail to mogwari2000@yahoo.com (Subject : PUE 3141)
  • For requesting additional office hours requested via E-Mail to rkiruki@uonbi.ac.ke (Subject : PUE 3141)

Course Outline

Week Content Tasks
1 Overview of digital logic design methodology  
2 Hardware Description Languages (HDL): VHDL  
3 Synthesis  
4 Design and synthesis of data path controllers and floating point processors  
5 Programmable Logic and storage devices  
6 Post-synthesis designs, simulation and testing of processors  

Course Description

  • Overview of digital logic design methodology, Review of combinational and sequential logic designs with Flip Flops (FF), Finite State Machines (FSMs); Hardware Description Languages (HDL): VHDL code structure and syntax; Definition of VHDL’s concurrent and sequential modes. Concurrent and sequential statements in VHDL. A systematic review of VHDL’s data types and data attributes. Signals and variables in VHDL. Logic design with VHDL; Logic Design with Behavioural modelling, Behavioural, data flow, and structural modelling of VHDL; Synthesis: Combinational logic, sequential logic, FSMs, Control structures, Design Traps; FSMs and the corresponding VHDL coding techniques. Design and synthesis of data path controllers and floating point processors: partitioned sequential machines, Complex Instruction Set Computers (CISC), Reduced Instruction Set Computers (RISC) Stored Program Machine (SPM), Universal Asynchronous Receiver and Transmitter (UART); Programmable Logic and storage devices, PAL, programmability and complexity of PLDs, FPGAs, embeddable and programmable IP cores for system-on-a-chip, FPGA design with HDLs, FPGA synthesis; algorithms and architectures for digital processors and arithmetic processors: digital filters and signal processors, Controllers, Building blocks, pipelined architectures, buffers; Post-synthesis designs, simulation and testing of processors: design validation, timing verification, fault simulation and collapsing, design for testability.

Motivation and Goals

  • At the end of the course, the student should be able to;
      1. Apply HDLs to design combinational and sequential logic circuits
      1. Apply system-on-chip (SoC) design methodologies, including high-level synthesis and partial run-time reconfiguration in the design of digital integrated circuits
      1. Design, verify and test working circuits suitable for Application-specific Integrated Circuit (ASIC) and/or FPGA implementation

Prerequisites

Grading Policy

  • Based on the University rules: there will be two in-class paper based exams (first & second mid-terms) in addition to the final exam. For all exams, exact dates and times are to be scheduled soon. However, our exam weights are:
    • First mid-term : 20%
    • Second mid-term : 20%
    • Final Exam: 40%
  • Class Activities Including:
    • Homework Assignments & Pop Up Quizzes: 15%
    • Attendance and Participation 5%

      Course Schedule

  • Schedule

Course Tools

References

Sections